Principal Physical Verification Engineer
Celero Communications, Inc.San Jose, California, United States · Posted 11 days agoDescription
Celero Communications, Inc. is an exciting and fast-growing semiconductor startup developing high-performance coherent digital signal processors (DSPs) for optical interconnects used in large-scale AI infrastructure. Celero's goal is to enable higher-bandwidth, lower-power optical connectivity between AI clusters and data centers.
We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness. The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs. You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.
Locations: San Jose, CA (preferred) or Irvine, CA (HQ)
Key Responsibilities
Team & Project Leadership
• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks
Physical Verification Ownership
• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules
Cross-Functional Collaboration
• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews
Required Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications
Proven hands-on experience with:
• Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV
Strong expertise in:
• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration
Preferred Qualifications
• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)
Similar jobs
Est. 200,000 USD
Celero Communications, Inc. is an exciting and fast-growing semiconductor startup developing high-performance coherent digital signal processors (DSPs) for optical interconnects used in large-scale AI infrastructure. Cel…
Est. 200,000 USD
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We…
Est. 200,000 USD
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. We…
Est. 200,000 USD
We are seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the…
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute…
Est. 200,000 USD
We are seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the…
Est. 175,000 USD
About The Role Celero is seeking an experienced Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking.…
Est. 300,000 USD
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify inn…
Est. 300,000 USD
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify inn…
Est. 200,000 USD
ASIC Design Engineer – DSP / Analog / SerDes Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Ou…
Est. 200,000 USD
ASIC Design Engineer – DSP / Analog / SerDes Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Ou…
We are seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the…
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semicondu…
Est. 200,000 USD
Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal…
Est. 212,500 USD
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this poss…
We are seeking a Senior Analog Layout Design Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the An…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Est. 227,500 USD
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this poss…
ASIC Design Engineer – DSP / Analog / SerDes Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Ou…
Est. 200,000 USD
Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal…
Est. 140,000 USD
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this poss…
Est. 245,000 USD
Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting…
Key Responsibilities Take full ownership of RTL-to-GDSII execution on complex designs, driving PPA and quality-of-results metrics to closure with minimal supervision. Lead methodology and solution-focused discussions wit…
Est. 170,000 USD
Role Overview We are seeking a highly experienced Senior or Staff Analog/Mixed-Signal IC Designer to join a world-class semiconductor team. The ideal candidate brings deep expertise in high-speed analog circuit design—sp…
Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal…
The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture,…
Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semicondu…